Introduction to SystemVerilog. Simple test bench template

Simple test bench template

　Make a note of a simple test bench template.

Simple test bench templete(SampleOfTb.sv)

/**
 * SampleOfTb.sv */
**/

`timescale 1ps/1ps

module SampleOfTb;

/* Define Clock cycle */
parameter CYCLE = 10;

/* Define the signals */
 logic clk;
 logic reset;

/* Instantiate module */
ModuleName InstanceName(.PortName0(SignalName0),
                        .PortName1(SignalName1),
		        .PortName2(SignalName2));

/* Implicit port declaration of SystemVerilog */
ModuleName InstanceName(.*);

/* Clock Generation */
always #(CYCLE/2) clk = ~clk;

/* Input the test vector to the circuit */
initial
begin
    $display("=== Start Of Simulation. ===");
    SYSTEM_RESET();

    // Input the test vector

    $display("=== End Of Simulation. ===");
    $finish;
end

/* System Reset */
task SYSTEM_RESET;
    #0 clk = 1'b0;
    #(CYCLE/2) reset = 1'b1; 
    #(CYCLE/2) reset = 1'b0; 
endtask

/* Display Signals */
task DISPLAY_SIGNAL;
    $display("Time:%dns : CLK:%d", $time,clk);
endtask

endmodule