Verilog/SystemVerilog $display

About $display

　Note about Verilog/SystemVerilog system task $display.

Format of $display

$display("Format", Argument0,Argument1...)

Sample code

/* test_display.sv */
module test_display();

logic[15:0] x = 16'hffff;

initial
begin
    display(x);
end

task display(logic [15:0] x);
    begin
	$display("########################");
	$display("x(Binary) = %b", x);
	$display("x(Hex) = %h", x);
	$display("x(Decimal) = %d", x);
	$display("########################");
    end
endtask
endmodule

Execution result

########################
# x(Binary) = 1111111111111111
# x(Hex) = ffff
# x(Decimal) = 65535
########################

Escape sequence

Format	Description
\n	New line
\t	Tab
\\	Output "\"
\"	Output "
\ddd	Character output by ASCII (octal number)
%%	Output "%"
%b or %B	Binary number
%d or %D	Decimal number
%e or %E	Index
%f or %F	Real number
%g or %G	% e,% f, output the one with the smaller number of digits
%h or %H	Hexadecimal
%l or %L	Library bind information
%m or %M	Hierarchy
%o or %O	Octal number
%s or %S	String
%t or %T	Time
%u or %U	Binary output of 0 and 1 (X, Z are 0)
%v or %V	Signal strength
%z or %Z	Four-value output of 0, 1, X, Z