Introduction to SystemVerilog. Flip-flop (FF)

フリップフロップ（FF）

SystemVerilogで各種FFを記述してみる。

D-FF(dflfl.sv)

/* dflfl.sv */
module dflfl(input  logic d,
             input  logic clk,
	     input  logic reset,
             output logic q);

always_ff @(posedge clk or posedge reset)
begin
    if(reset) q <= 1'b0;
    else      q <= d;
end
endmodule

同期式RS-FF(rsflfl_sync.sv)

/* rsflfl_sync.sv */
module rsflfl_sync(input  logic clk, 
                   input  logic reset,
	           input  logic set,
	           output logic q,
	           output logic qb);

always@(posedge clk) begin
  if (reset)       q <= 0;
  else if (set)    q <= 1;
end

assign qb = ~q;
endmodule

JK-FF(jkflfl.sv)

/* jkflfl.sv */
module jkflfl(input  logic clk,
              input  logic j,
	      input  logic k,
	      input  logic reset,
	      input  logic set,
	      output logic q);

always_ff @(posedge clk or posedge reset or posedge set)
begin
  if (reset)       q <= 0;
  else if (set)    q <= 1;
  else 
    case ({j, k})
      2'b00 : q <= q;
      2'b01 : q <= 0;
      2'b10 : q <= 1;
      2'b11 : q <= ~q;
    endcase
end
endmodule

T-FF(tflfl.sv)

/* tflfl.sv */
module tflfl(input  logic clk, 
             input  logic reset,
	     output logic q);

always_ff @(posedge clk or posedge reset)
begin
  if (reset)  q <= 1'b0;
  else        q <= ~q;
end
endmodule